1. Field of the Invention
This invention relates to protection circuitry for preventing damage to bipolar and bipolar-CMOS integrated circuits (ICs) due to electrical overstress (EOS) events, especially those arising from electrostatic discharge (ESD) events.
1. Description of the Related Art
EOS on an IC results from an external source discharging large transient voltages over a short period of time onto a terminal of the IC. EOS events include not only very fast transients such as ESD events which may result from human contact with the IC, but also slower transients such as power-up glitches. The purpose of an EOS protection circuit is to prevent damage to ICs during EOS events, especially those arising from ESD. It is desirable for EOS protection circuits to draw negligible leakage currents in their inactive state so that the IC can operate uninterrupted, and to quickly activate and divert current away from the IC when its voltage tolerance is exceeded as occurs during EOS events. A significant feature of an EOS protection circuit is its activation voltage, which should ideally be just above the highest breakdown voltage of the transistors on the IC. This ensures that the protection circuit is in the inactive state during normal IC operation, but activates at the lowest possible voltage beyond the transistor operating limits. Furthermore, EOS circuits should dissipate high peak voltages and currents without damage to either the IC or the EOS circuit. Therefore, in the active state it is desirable that the EOS circuit have a low impedance and a low holding voltage to dissipate very high EOS peak currents.
An existing EOS protection circuit is disclosed in U.S. Pat. No. 5,212,618, O'Neill et al., May 18, 1993. In one embodiment, the circuit includes a first npn transistor which has its emitter connected to an input terminal and, through a base resistance, to its base. A second npn transistor has its emitter connected to the substrate and to its base through another resistor. The collectors of the two transistors are formed by a single n-doped tub. When a positive voltage is applied to the input terminal, the second transistor's p-type base forward biases to the tub, but the tub will not conduct until its voltage exceeds the second transistor's collector-emitter breakdown voltage with the base shorted to the emitter (BVces). When the tub conducts, the second transistor turns on, clamping the tub voltage to its collector-emitter breakdown voltage with the base open-circuited (BVceo) or less. When a negative voltage is applied to the input terminal, two diodes form. The first diode is from the second transistor's base to the tub and turns on when the tub is below the substrate by the forward-biased base-emitter junction voltage (1 Vbe). The second diode is the inherent substrate-to-tub diode which will forward bias when the tub is below the substrate by 1 Vbe. The two diodes conduct when the first transistor's emitter is pulled negative with respect to the tub by the first transistor's BVces. When the diodes turn on, the first transistor turns on and clamps the tub voltage to its emitter at the collector-emitter breakdown voltage with the base open circuited (BVceo) or less.
The circuit thus operates as an open circuit until a voltage equal to plus or minus BVces (typically 60 to 80 volts) is applied to the input pin. Once on, the circuit has a holding voltage of plus or minus BVceo (typically 40-50 volts) plus 1 Vbe. A drawback of this circuit is that the holding voltage is high. During high ESD currents, power dissipation will be high and potentially damaging to the IC being protected. Another disadvantage is that the circuit is connected between a circuit terminal and the substrate, offering no protection when an ESD occurs between two circuit terminals.